| 摘要 |
The generator includes a clock (H) which provides base clock signals (CK0) and second clock signals (CK1) at 2 to the power p times less than the base frequency. For each base clock signal, a first logic operator (L1) provides a first binary output value (s1) from binary values (a1,a2) extracted from first and second calculators (CQ,CR) and a second logic operator (L2) gives p second binary output values (s2-s4) from similarly extracted binary values (b1,c1,b2,c2). A first memory (RD1) memorises the first binary output values for 2 to the power p consecutive base clock signals and a selection device (MS) selects one of the memorised binary values for each second clock signal to form the output word (DS).
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