| 摘要 |
PURPOSE: To reduce test circuit scale by sharing the circuit with a circuit to be ordinarily used in the case of performing singly the test of a processor element(PE) and to provide an operation processing function for dealing with data in various formats by using the same circuit. CONSTITUTION: In order to selectively output the intermediate result of the PE or a numerical value '0' by both enable signals (Xm) and (Yn), a selector 206 inside each PE as the essential part of the array processor can set into an arithmetic state for adding the intermediate result of PE to the output value of the PE on the preceding stage and outputting the result to the PE on the next stage and a non-arithmetic state for outputting the output value of the PE on the preceding stage to the PE on the next stage as it is. Thus, when the PE as the object of test is set in the arithmetic state and the other PE is set in the non-arithmetic state, at the time of an ordinary operation, only the arithmetic result of the PE as the test object is transferred and outputted through an AE-BUS for transferring the arithmetic target value of a processor array, so that the operation test of PE as the test object can be performed. |
