发明名称 POWER CONSUMPTION REDUCING DEVICE OF LOGIC CIRCUIT MOUNTED DEVICE
摘要 <p>PURPOSE: To reduce the power consumption of the logic circuit mounted device which operates with a system clock. CONSTITUTION: The logic circuit mounted device which operates with the system clock consists of an oscillation stop means consisting of a monostable multivibrator 13 which stops the oscillation of an oscillator X11 for the clock and a switching circuit 14 and a restart means which restarts the oscillation of the clock in response to the generation of the event and includes a time constant circuit resistor R11 and a capacitor C11 provided associatively with the said monostable multivibrator 13.</p>
申请公布号 JPH08147065(A) 申请公布日期 1996.06.07
申请号 JP19940289720 申请日期 1994.11.24
申请人 MATSUSHITA ELECTRIC IND CO LTD 发明人 SUZUKI SHOJI;KOBAYASHI JUN
分类号 G06F15/78;G06F1/04;H04B1/034;(IPC1-7):G06F1/04 主分类号 G06F15/78
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