发明名称 DIVISION ARITHMETIC OPERATION DEVICE
摘要 PURPOSE: To calculate a remainder with a simple constitution with respect to the remainder arithmetic device which calculates a multiplier for divisor in accordance with a predictive quotient as the predictive value of a quotient part to calculate a new partical remainder in accordance with multibit operation processing and repeats not only correction of the predictive quotient based on the partial remainder but also generation of a new predictive quotient to execute the floating-point division processing. CONSTITUTION: A save register means 19 which saves the partial remainder obtained by division processing just before a multibit quotient including a rounding position, a rounding means 16 which subjects the multibit quotient including the rounding position to rounding processing, and a normalizing means 18 which executes the justification processing of the partial remainder calculated by the partial remainder saved by the save register means 19 and the divisor multipliere for divisor derived from the multibit quotient obtained by the rounding means 16 are provided, and the processing result of the normalizing means 18 is outputted as the remainder obtained by dividing the dividend by the divisor.
申请公布号 JPH08147146(A) 申请公布日期 1996.06.07
申请号 JP19940289401 申请日期 1994.11.24
申请人 FUJITSU LTD 发明人 NAGATA TOSHIMITSU
分类号 G06F7/52;G06F7/483;G06F7/535;G06F7/72 主分类号 G06F7/52
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