| 摘要 |
Method and apparatus for a scalar data cache in a scalar/vector supercomputer. The scalar data cache comprises a cache array (11c) and a cache controller. The cache array comprises a plurality of cache frames; each cache frame comprises a plurality of cache lines; and each cache line comprises a plurality of data words. The cache controller performs a broadside compare of the reference address against all addresses held in the cache, and translates the reference address into a cache-array address. For each cache line, there is a corresponding cache-line validity indication which is set "valid" only when every data word in the cache line contains valid data. A cache-line validity comprator operates to provide a cache-line-hit indication if a data word requested is in a valid cache line. A cache load controller is described for loading data from a common memory into every data word of a cache line and for marking the cache line "valid". For at least one of the plurality of scalar registers (120, 130), a cache accessor is described for providing fetch access to the data words in the cache array, and for providing write-through-cache capability to the data words in the cache array. Thus only scalar registers can fetch from and write-through to the cache (110), while all other registers (140, 150, 160) must access data directly from a common memory (602).
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