发明名称 |
A NOVEL PROCESSOR HAVING SHIFT OPERATIONS |
摘要 |
The processor (109) includes a decoder (202) being coupled to receive a control signal (207). The control signal has a first source address, a second source address, a destination address, and an operation field. The first source address corresponds to a first location. The second source address corresponds to a second location. The destination address corresponds to a third location. The operation field indicates that a type of packed data shift operation is to be performed. The processor further includes a circuit (203) being coupled to the decoder. The circuit is for shifting a first packed data being stored at the first location by a value being stored at the second location. The circuit is further for communicating a corresponding result packed data to the third location.
|
申请公布号 |
WO9617289(A1) |
申请公布日期 |
1996.06.06 |
申请号 |
WO1995US15682 |
申请日期 |
1995.12.01 |
申请人 |
INTEL CORPORATION |
发明人 |
PELEG, ALEXANDER;YAARI, YAAKOV;MITTAL, MILLIND;MENNEMEIER, LARRY, M.;EITAN, BENNY |
分类号 |
G06F7/00;G06F5/01;G06F7/76;G06F9/30;G06F9/315;G06F9/38;(IPC1-7):G06F5/01 |
主分类号 |
G06F7/00 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|