发明名称 MICROPROCESSOR WITH PACKING OPERATION OF COMPOSITE OPERANDS
摘要 A processor includes a first register (209) for storing a first packed data, a decoder (202), and a functional unit (203). The decoder has a control signal input (207) for receiving a first control signal and a second control signal. The first control signal is for indicating a pack operation, and the second control signal is for indicating an unpack operation. The functional unit is coupled to the decoder (202) and the register (209). The functional unit performs the pack operation and the unpack operation using the first packed data as well as move operation.
申请公布号 WO9617291(A1) 申请公布日期 1996.06.06
申请号 WO1995US15713 申请日期 1995.12.01
申请人 INTEL CORPORATION 发明人 PELEG, ALEXANDER;YAARI, YAAKOV;MITTAL, MILLIND;MENNEMEIER, LARRY, M.;EITAN, BENNY
分类号 G06F9/30;G06F9/302;G06F9/315;G06F9/318 主分类号 G06F9/30
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