STEERED FREQUENCY PHASE LOCKED LOOP

摘要

A Steered Frequency Phase Lock Loop (SFPLL) comprises a phase loop that functions like a normal phase locked loop (PLL) and locks to the input signal, and a frequency loop that uses a reference frequency to influence the phase loop and effectively confines the output frequency of the phase loop and the SFPLL to be in a range of frequencies close to the reference frequency. The reference frequency is chosen to be very close to the input signal frequency that it is desired the SFPLL lock to. The SFPLL comprises a phase detector (10), a frequency detector (22), first and second gain components (12, 24), first, second and third filter components (14, 18, 26), a summer (16) and a voltage controlled oscillator (VCO) (20). By a judicious choice of the gains in the phase and frequency loops the SFPLL can be designed so that the range of frequencies to which the SFPLL will lock can be confined to an arbitrarily small region around the reference frequency (φ'r). Applications of the SFPLL include demodulation in CW modulation systems and timing recovery from NRZ data. Three advantages of the SFPLL are that the output frequency is equal or close to the reference frequency when no input signal is present, and the range of frequencies to which the SFPLL can lock is confined to a region around the reference frequency, and the phase and frequency instabilities of the VCO can be reduced.