| 摘要 |
<p>A QAM demodulator (400) that samples an IF input modulated with data at a fractional complex sampling rate between one and two times the data rate. The use of a fractional sampling rate significantly reduces the number of components necessary to implement the demodulator, particularly in the equalizer section (414, 416) of the demodulator (400) which corrects for channel distortion. The fractional sampling rate demodulator architecture of the invention provides a significant reduction in integrated circuit surface area needed in a VLSI implementation.</p> |
