Digital video data memory addressing circuit for MPEG video processing

摘要

The memory address space is arranged as a main area with linear matrix form X-Y-addressing and multiple rectangular sub-areas with two-stage addressing. The horizontal or vertical memory size of each area is chosen so that exactly 2n elements, where n is integral, may be stored in a column or row.The data ordering in the sub-areas is such that it may be selected using a comparator, so that in addition, multiple comparators may be used.