In an FIFO memory, a word line pointer (4) sequentially specifies word lines (8) in accordance with the first clock signal (CLK1) outputted from a clock generator (3). When the last pointer (5) outputs a last line access signal (PAS3) indicating that the last word line (8E) has been accessed, a control flag generator (2) detects that the last address has been accessed on the basis of the last line access signal (PAS3) and a clock signal (COS) in synchronization with the first clock (CLK1) and outputs a clock control signal (CCNT) in accordance with a timing of the detection. The clock generator 3 stops counting a reference clock signal (CLK0) in response to the clock control signal (CCNT). Thus, the access to a memory cell array of the FIFO memory is stopped in accordance with the number of effective pixels of inputted video signals, and thereby reduction in memory capacity and in power consumption can be achieved.
