| 摘要 |
<p>A successive approximation circuit and method are disclosed for digitally approximating a moving signal (16) using an analog-digital converter (ADC) (18) and a comparator (14) for generating a comparison signal from the moving signal. An estimate register (34) and a bit and conversion control circuit are provided, with the bit and conversion control circuit (23) including a bit control circuit (30) and a conversion control circuit (24), where the bit control circuit (30) adjusts a current plurality of output bits (38) to compensate for an error due to a slew rate to generate the digitally approximated moving signal. An adder is included for adding the control value to the current plurality of output bits to generate the next plurality of output bits. Alternatively, an adjustment selection circuit and a logic chain circuit are included. A successive approximation circuit and method are also disclosed for reducing noise in the approximation including a bit tap circuit having a tap converter, which responds to the plurality of output bits and an adjustment circuit for adjusting the bit taps to have reduced noise in the output estimate. The bit tap circuit converts the adjustment signal to an extra least significant bit (LSB) tap of the final plurality of bit taps. Alternatively, the bit tap circuit converts the adjustment signal to a first bit tap corresponding to a most significant bit (MSB) of the plurality of output bits. In another embodiment, the bit tap circuit includes a plurality of AND gates and a plurality of OR gates. <IMAGE></p> |
