| 摘要 |
The turn around time required for fabricating a semiconductor integrated circuit from initial conception through packaging may be dramatically reduced by testing the electrostatic integrity of the integrated circuit during fabrication rather than after packaging. In such a method, an electrostatic test device is formed on the same substrate on which the integrated circuit is formed. The test element may or may not comprise a portion of the integrated circuit itself, and a plurality of such test elements may in fact be formed along scribe lines in the wafer. Prior to dicing of individual integrated circuits, the electrostatic withstand capacity of the test element is determined by locating the power required to destroy the test element. The electrostatic destruction withstanding value of the integrated circuit is then derived from the maximum nondestruct power of the test element. Thus, an inspection step for electrostatic withstand capacity may be performed during fabrication, and need not await final packaging.
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