| 摘要 |
A semiconductor memory device having a test circuit includes voltage detection circuits (120, 220) for detecting a test mode when a voltage higher than a normal use voltage is applied to a terminal (101, 201). When one voltage detection circuit (120) detects a test mode, a voltage switching circuit (130) renders a MOS transistor (111) conductive, a resistance (115) connected in parallel to the MOS transistor is short-circuited and a voltage lower than (1/2xVcc) is applied to a bit line voltage supply line (9). Alternatively, when the other voltage detection circuit (220) detects the test mode, a voltage switching circuit (230) renders a MOS transistor (211) conductive, a resistance (114) connected in parallel to the MOS transistor is short-circuited, and a voltage higher than (1/2xVcc) is applied to the bit line voltage supply line. Thus, by applying a voltage higher or lower than that for normal use on a bit line, a memory cell having a small margin can be tested in a short period of time. |
