发明名称 Processor system having an external arithmetic device for high speed execution of computation of data
摘要 A processor system has a processor for outputting an instruction including a first data to be used for arithmetic process, a multiplier for executing arithmetic operation including a first memory for storing the instruction output from the processor, a second memory for storing second data selected based on the instruction, and an arithmetic circuit for executing arithmetic operation between the first data and the second data, an address bus for connecting the processor and the multiplier, a data bus for transferring the second data and arithmetic result obtained by the arithmetic circuit. The multiplier is capable of executing the arithmetic operation between the second data items or between the first data and the second data, the arithmetic result is output to the second memory or the data bus under the control of the instruction.
申请公布号 US5524259(A) 申请公布日期 1996.06.04
申请号 US19930053565 申请日期 1993.04.28
申请人 KABUSHIKI KAISHA TOSHIBA 发明人 MIYAMORI, TAKASHI;KOGA, MIHO
分类号 G06F7/57;G06F9/302;G06F13/40;G06F13/42;(IPC1-7):G06F13/16;G06F13/36 主分类号 G06F7/57
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