| 摘要 |
PURPOSE: To constitute a high-speed clock generation circuit only by a digital circuit by providing an edge detection pulse generation circuit and an asynchronous reset oscillator for starting the generation of high-speed clocks by the rise of edge detection pulses. CONSTITUTION: A rise edge detection pulse generation circuit 11 detects the rise edge of trigger signals 10a to be the actuation signals of the delay operation of this variable delay circuit 600 and generates the edge detection pulses 11a of a specified pulse width. Then, the asynchronous reset oscillator 12 is reset by the pulses 11a. At the time, reset is asynchronously performed regardless of the operating state of the oscillator 12. The oscillator 12 maintains an L state when the pulses 11a are in an H state and starts an oscillation operation when they are shifted to the L state. In such a manner, by constituting the high-speed clock generation circuit 100 for the variable delay circuit by the circuit 11 and the oscillator 12, the circuit 100 can be constituted by the digital circuit only. |
