| 摘要 |
<p>PURPOSE: To provide a signal processor which is decreased in circuit scale and reduced in the number of constituent components without sacrificing characteristics of convolution processing. CONSTITUTION: This signal processor consists of a scanning converting circuit 1 which divides a two-dimensional digital data array into plural blocks and converts input data obtained by scanning the blocks, one by one, into the scanning order of an array format, data buffers 3-1 and 3-2 which delay the output data from the scanning converting circuit 1, S/P converting circuits 2-1, 2-2, and 2-3 which output output data from the scanning converting circuit 1 or data buffers 3-1 and 3-2 in parallel, a shift register array 4 which stores the data from the S/P converting circuits, a data selector 7 which takes data out of the shift register array 4, and a convolution processing circuit 8 which performs the convolution processing by using the taken-out data and a two-dimensional coefficient array.</p> |
