| 摘要 |
PURPOSE: To provide a system for easily detecting coincidence at high speed by allowing the existence of plural non-coincident elements in an input code in comparison with a desired code. CONSTITUTION: This system is provided with an exclusive OR circuit 11, error number counting circuit 12 constituted by hierarchically arranging plural adder circuits 121a-121d, 122a and 122b over plural stages, numerical value setting circuit 14 for setting a prescribed threshold value and numerical comparator circuit 13. Then, the input code and the desired code are inputted to the exclusive OR circuit 11, the error number counting circuit 12 inputs the output of the exclusive OR circuit 11 and counts the number of non-coincident elements, and the code coincidence is detected while allowing that the number of non- coincident elements is less than the threshold value set by the numerical value setting circuit 14. Further, the plural adder circuits 121a-121b, 122a and 122b in the error number counting circuit 12 are respectively composed of a full adder circuit 123 and the carry input of the full adder circuit 123 is allocated to one part of the input of the error number counting circuit 12. |
