| 摘要 |
<p>PURPOSE: To prevent influence on reading operation by cutting between a drain and a corresponding data line by a row selecting MOSFET even when the memory cell of a depleted state exists in a column address to be read of a memory array. CONSTITUTION: Row selecting MOSFETNs 0 to Nsm are provided between data lines DO to D7 corresponding to the drains of 2-layer gate structure memory cells Nc0 to Ncm, etc., for forming a memory array of a flash memory, etc. Even when the memory cell of depleted state exists in designated eight data lines DO to D7, i.e., the column address to be read, the data lines corresponding to the drains are cut by the row selecting MOSFET, thereby preventing the influence to the reading operation. Thus, the reading of the flash memory is normalized to enhance the product yield.</p> |
