PCI/ISA Bridge Having an Arrangement for Responding to PCI Bridge Address Parity Errors for Internal PCI Slaves in the PCI/ISA Bridge

摘要

A peripheral controller interconnect/industry standard architecture (PCI/ISA)bridge is coupled between the PCI and ISA buses in a computer system. A PCI master in the system asserts address and address parity information on the PCI bus to initiate a master-slave transaction over the PCI bus. The bridge includes logic for comparing the address and the address parity information and generating an address parity error signal when there is an address parity error. The bridge also includes a PCI slave that receives the address parity error signal and generates a target-abort signal in response if the PCI slave has already claimed the address by asserting a device select signal. The bridge also includes logic that prevents the target-abort signal from propagating to the PCI bus whenever this logic receives both the address parity error signal and the device select signal. This allows the master to perform a master-abort and prevents the PCI slave on the bridge from performing a target-abort when there is an address parity error.