Anordnung mit einer Master-Einheit und mehreren Slave-Einheiten

摘要

In an arrangement with a master unit and a plurality of slave units (1, ..., 5) to which the master unit has read/write access with addresses via a bus (SYB) with address, data and control lines (SL, AL, DL), the setting of the access addresses is simplified in that the slave units (1, ..., 5) each have an address register (BC) activatable by an address setting signal (SEL0, SEL1, SEL2, SEL3, SEL4), the address setting signals (SEL0, SEL1, SEL2, SEL3, SEL4) can be isolated under clock control during an address setting stage, the master unit writes the access address into the address register (BC) of the slave unit via the data lines, the address setting signal (SEL0, SEL1, SEL2, SEL3, SEL4) of which has been isolated, and the slave unit (1, ..., 5) isolates the address setting signal (SEL0, SEL1, SEL2, SEL3, SEL4) of the next slave unit (1, ...) after address setting. The invention is applied to stored-program controls.