| 摘要 |
PURPOSE: To hardly cause step-out and to secure a stable clock signal reproducing operation relating to a clock signal reproducing circuit (clock recovery circuit) for reproducing clock signals from data signals such as NRZ signals or the like. CONSTITUTION: This circuit is provided with a PLL circuit 22 operated so as to frequency synchronize signals S24 with the signals S191 and a PLL partial circuit 23 operated so as to phase synchronize the signals S114 with the data signals DATA for which the phase synchronization operating speed is made lower than the frequency synchronization operating speed of the PLL circuit 22. The signals S24 are frequency synchronized with the signals S191 by the operation of the circuit 22 first, then, the signals S114 are phase synchronized with the data signals DATA by the operation of the circuit 23 and the signals S114 are outputted as the clock signals CLK reproduced from the data signals DATA. |
