| 摘要 |
A high speed analog signal sampling system. The system comprises a timing chain having a plurality of delay elements arranged in series and a sample rate multiplier having a delay lock control system responsive to the outputs of first, second and third parallel delay elements in the sample rate multiplier to control the delay of the second parallel delay element so that its strobe signal output occurs one-half the time between the strobe signal outputs of the first parallel delay element and the third parallel delay element. The first, second and third parallel delay elements are the first three parallel delay elements of the timing chain, and a control signal of the delay lock control system is used to adjust and control the amount of delay introduced by every other parallel delay element after the second parallel delay element. The second and third parallel delay elements straddle one of the series delay elements in the timing chain, while the first parallel delay element has the same input as the second parallel delay element. The delay lock control system employs a sampling circuit which samples the strobe signal output of the first parallel delay element in response to an output of the second parallel delay element and which samples the strobe signal output of the second parallel delay element in response to an output of the third delay element, and further employs a control circuit which filters the difference between those two sampled output signals and provides that filtered difference as the control signal.
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