| 摘要 |
A shift register which is stably operable even under low power voltage and including a first transfer gate NTM1 connected to a data input terminal DIN1, second and third transfer gates NTM2 and NTM3 connected in series to a ground line, a pair of inverters IVM1 and IVM2 connected in the opposite orientation between the output terminals of the first and third gates, and fourth and fifth transfer gates NTS1 and NTS2 connected in parallel with respect to the outputs of the pair of inverters IVM1 and IVM2. The shift register further includes a pair of inverters IVS1 and IVS2 connected in the opposite orientation between the output terminals of the fourth and fifth gates. The gate terminal of the second gate is connected to the data input terminal, a first clock signal MCLK is input into the gate terminals of the first and third gates, and a second clock signal SCLK, in which the phase differs from the first clock signal, is input into the gate terminals of the fourth and fifth gates.
|
