Phase detection reset in phase locked loops used for direct VCO modulation

摘要

A phase-lock loop (PLL) includes a switch for opening the loop (e.g. for direct modulation of its voltage-controlled oscillator (VCO) during transmission of an intermittent signal such as data bursts) and has a phase comparator which can be selectively initialized (e.g. by setting to a programmed value or resetting to zero or terminal count value the reference and/or feedback signal frequency dividers) so that upon "re-closing" of the loop the PLL will achieve phase-lock within a predetermined amount of time. When the loop is opened, the VCO's dc ("phase-lock") control voltage can be maintained so as to help ensure that phase-lock will be achieved within the desired amount of time.