| 摘要 |
Features which support conditional execution and sequencing are employed in concert with a centralized-control, single-instruction, multiple data integrated video signal processor, thus adapting efficiently to the high degree of parallelism inherent in this type of video signal processing systems. A three-level prioritization scheme is used to handle the input/output data stream to improve the throughput of the processor, including provisions for distinguishing between same-priority events occurring at different times, and ensuring that in such cases the requested operations occur in the same temporal order as the respective requests.
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