发明名称 |
Non-volatile semiconductor memory device allowing fast verifying operation |
摘要 |
A bit line reset transistor resets every second bit line of a plurality of bit lines to be write-verified. At this time, a transfer gate disconnects a column latch from the unreset bit line. Then, the unreset bit line is precharged in accordance with data of the column latch, while applying a verify voltage to a word line. Then, a source line transistor grounds a source line, and the bit line is connected to the column latch, so that data corresponding to a value of a threshold voltage of the memory cell is held by the column latch, and a write verifying operation is performed.
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申请公布号 |
US5521864(A) |
申请公布日期 |
1996.05.28 |
申请号 |
US19950385866 |
申请日期 |
1995.02.09 |
申请人 |
MITSUBISHI DENKI KABUSHIKI KAISHA |
发明人 |
KOBAYASHI, SHINICHI;NAKAI, HIROAKI;ISHII, MOTOHARU;OHBA, ATSUSHI;FUTATSUYA, TOMOSHI;HOSOGANE, AKIRA |
分类号 |
G11C17/00;G11C16/02;G11C16/34;G11C29/50;(IPC1-7):G11C11/34 |
主分类号 |
G11C17/00 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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