| 摘要 |
<p>A circuit including a data formatter (70) for receiving desired information associated with a data packet and arranging the bits into a format for transfer to a memory (80), a memory for storing the desired information for later access by a microprocessor (20), and a controller (90) for selectively transferring and writing the desired information from the data formatter to said memory. The circuit provides improved performance by storing only the desired information for a data packet having an error. That is, information internal to the data packet itself, such as the source address, and information external to the data packet, such as the repeater port number, in addition to data packet error information, such as error conditions, may be stored as an error statistic in a memory for a microprocessor to read at its leisure. The present invention has an advantage of being more efficient and economical in gathering error statistics of data packets, as well as providing an increased capability to determine sophisticated error statistics on a packet-by-packet basis.</p> |
