发明名称 Resist pattern model evaluation method for semiconductor component mfr.
摘要 The method involves forming a mask pattern (1) by exposing a resist on a wafer. The two dimensional light distribution on the wafer (4) is then calculated based on the mask pattern and the exposure conditions (2). The light intensities at positions around a specific optional position in the plane of the wafer (3) are then used as a basis for the calculation, the distances between the optional and peripheral positions being allowed for. The cumulative addition of the effect of the light intensities on the exposure energy at the optional position are then used. A two dimensional latent image development intensity at the optional position is then calculated (40) and the distribution of the intensity in the two dimensional plane determined (41).A threshold value is then determined as a function of the illumination level and development conditions. The contour along which the threshold level is maintained within the distribution of the latent image development intensity is determined (42) and the pattern established by this contour is the evaluation for the model of the resist pattern (43).
申请公布号 DE19542818(A1) 申请公布日期 1996.05.23
申请号 DE19951042818 申请日期 1995.11.16
申请人 SONY CORP., TOKIO/TOKYO, JP 发明人 TSUDAKA, KEISUKE, KANAGAWA, JP
分类号 G03F7/20;H01L21/027;(IPC1-7):G03F7/20;H01L21/312 主分类号 G03F7/20
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