Reset generation circuit to reset self resetting CMOS circuits

摘要

The circuit includes a charging device which charges a node to a predetermined voltage in response to a RESET signal. A discharge device is connected between the node and ground and includes a ground interrupt device which prevents discharge of the node. A latch connected to the node generates the RESET signal in response to discharge of the node. A clock input circuit has multiple paths with a first path connected to the ground interrupt device. A second path is connected to the discharge device. The ground interrupt device also enables discharge of the node in response to the RESET signal. The first path has a greater time delay than the second path, allowing the ground interrupt device to prevent node discharge while the charging device charges the node.