| 摘要 |
A digital output of a quasi-coherent detection circuit is M-th power multiplied and then processed by a set of digital filters to generate signals for coherent detection and clock interpolation. The digital output of the quasicoherent detection circuit is also fed, through a delay circuit, to coherent detection circuit which in turn processes the digital output of the quasi-coherent detection circuit, using the coherent detection signal. Timing error information indicative of the difference between phases of an interpolated clock and the interpolation signal determines the weighting factor of data interpolation channel filter which in turn interpolate and output coherent-detected data signal. |
