| 摘要 |
PURPOSE: To reduce the capacity of a ROM and to reduce circuit scale by providing a phase data generating circuit in the same period of a generated waveform, voltage generating part to be linearly changed in any specified cycle and ROM, adding these signals and processing them with phase data. CONSTITUTION: The outputs of a bit inverter 2 are data corresponding to the phases from '0' toπ/2. Next, a bit inverter 3 converts the phase data from '0' toπ/2 to data symmetrical to the axis ofπ/4 by performing the similar operation to the bit inverter 2, Thus, the outputs of the bit inverter 3 become the data corresponding to the phases from '0' toπ/4. A ROM 4 inputs output data Q of the bit inverter 3 and generates 1/2×(1+SIN2Q)<1/2> and a ROM 5 generates 1/2×(1-SIN2Q)<1/2> . An adder/subtracter 6 adds or subtracts the outputs of the ROM 4 and 5. A bit inverter 7 performs inverting/non-inverting processing corresponding to the value of half-wave rectified waveform data PHA[L] and sine waveform data SIN (1:M) of M bits can be provided.
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