| 摘要 |
PURPOSE: To reduce the scale of hardware by providing respectively specified product-sum operation means, coefficient switching means and serial/parallel conversion means. CONSTITUTION: This matrix arithmetic circuit 301 receive the three pieces of parallel input data Rin, Gin and Bin, multiplies the respective input data with prescribed coefficients supplied through switching circuits 302 to 304, performs addition among the multiplied respective input data and obtains the three pieces of serial output data R0, G0 and B0 corresponding to the three pieces of the parallel input data. Also, the switching circuits 302 to 304 switch the prescribed coefficients to be multiplied with the respective input data by a clock timing which is the three times of an input data rate at the time of computing the respective output data corresponding to the respective three pieces of the parallel input data. Also, a serial/parallel converter 305 converts the serial output data R0, G0 and B0 from the circuit 301 to parallel data and simultaneously outputs them. |
