发明名称 VARIABLE DELAY CIRCUIT
摘要 <p>PURPOSE: To provide a sufficient variable quantity by securing an amplitude and starting time required for the delay circuit by connecting an output buffer between a logic circuit and the first input terminal of a differential gate and connecting a capacitor through an external terminal to the output of this buffer. CONSTITUTION: The output of a logic circuit 10 is inputted to an output buffer 1, and that output is inputted to a non-inverted input terminal 3A of a differential gate 3. Besides, it is connected through an external terminal A to a capacitor 4, and the output of a D/A converter 2 is inputted to an inverted input terminal 3B. Since the amplitude of the signal of the logic circuit 10 inputted to the buffer 1 gets larger than that of an internal gate and the starting time of the buffer 1 is longer in comparison with that of the internal gate, the range of an output voltage by the control signal of the D/A converter 2 can sufficiently widely be secured even while considering a noise margin, and the delay time can be secured longer than the case of the internal gate. Further, the capacitor 4 is connected through the external terminal A, the starting time is made longer, and the delay amount can be further widened.</p>
申请公布号 JPH08130447(A) 申请公布日期 1996.05.21
申请号 JP19940290424 申请日期 1994.10.31
申请人 ANDO ELECTRIC CO LTD 发明人 SAWAI MORIYASU
分类号 H03K5/13;(IPC1-7):H03K5/13 主分类号 H03K5/13
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