Integrated circuit having clock-line control and method for testing same

摘要

An integrated circuit includes a plurality of interconnected circuit modules having memory elements and logic elements therein. The modules collectively perform the operations of the integrated circuit. However, rather than testing the entire circuit and limiting the degree of fault coverage, individual modules can be tested on a module by module basis. To facilitate testing at the module level, the circuit includes a plurality of control cells connected to respective ones of the modules. Each of the control cells preferably includes a shift register latch for retaining a data signal corresponding to whether the respective module is to be sequentially tested or temporarily disabled. The control cells further comprise a pass-through transistor network for passing the system clock to one or more of the modules under test and for withholding the clock from the modules not under test. The method of the present invention includes steps for disabling one or more modules which are not under test and enabling those modules which are to be tested. The enabled modules are then tested sequentially, preferably using one or more outputs from the disabled modules. Testing of the integrated circuit occurs on a module by module basis until all modules are tested.