发明名称 PLL CIRCUIT
摘要 PURPOSE: To speedily make a response to the switching of an input video signal by generating a frequency-dividing ratio based on the integral value of a phase comparison error between a reference input signal and a comparison signal. CONSTITUTION: When the reference input signal is switched, the comparison signal of a frequency nearest to the frequency of the reference input signal is generated. When the reference input signal is switched in such a case, a programmable frequency-dividing part 2 becomes the output state of the minimum frequency signal (reference signal) by the prescribed frequency-dividing ratio, for example. An A/D conversion part 5 generates voltage data obtained by converting the comparison error integral value (control voltage) of LPF 4 controlling VCO 1 into digital data and supplies it to ROM 7. ROM 7 refers to a look-up table where the comparison error integral value is made to correspond to frequency-dividing ratio, reads corresponding frequency-dividing ratio and supplies the frequency-dividing ratio data to the frequency-dividing part 2 via a control part 8. When various video signals are switched and inputted, the signal locked to the phase of the reference input signal can be generated at high speed.
申请公布号 JPH08125529(A) 申请公布日期 1996.05.17
申请号 JP19940255713 申请日期 1994.10.20
申请人 FUJITSU GENERAL LTD 发明人 OKADA KAZUO
分类号 H03L7/08;H03L7/10;H04L7/033 主分类号 H03L7/08
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