| 摘要 |
PURPOSE: To reduce the number of classification devices arranged in parallel. CONSTITUTION: Received picture elements are delayed in registers 21 -2m and a minimum value MIN is detected in a register 13, a comparator 14 and an AND gate 15 and a maximum value MAX is detected in a register 19, a comparator 20 and an AND gate 21. A subtractor 17 subtracts the minimum value MIN from the delayed picture elements, and a subtractor 22 calculates a dynamic range DR. A quantization circuit 51 conducts 1-bit ADRC based on the picture element from which the minimum value MIN is subtracted and the dynamic range DR and data latched in registers 52-66 are fed to a call generating circuit 67, from which a class code in 15-bits is outputted. |
