| 摘要 |
<p>PURPOSE: To adjust a delay time less than one stage of a buffer circuit through the use of a digital circuit by providing n-pieces of selection circuits and (n+1) input NOR/OR circuits. CONSTITUTION: If a signal I1 is outputted from the selection circuit SEL1 by delay time control signal S1 when the input signal I1 rises, the same signals are inputted to the respective inputs of a two-input NOR circuit NOR 1. A charge accumulated in the capacity of the gate of a transistor Tr3 is discharged to VSS through the drains and the sources of Tr1 and Tr2. The output terminal NNOR 1 of NOR 1 becomes 'L' from 'H' after delay time tal, and data output O1 becomes 'H' from 'L' after time tal obtained by adding the delay time of an invertor INV. When a signal VL is outputted from SEL1 by the signal S1, the signal of a terminal NNOR 1 becomes 'L' from 'H' after delay time ta0, and output O1 becomes 'H' from 'L'. When the signal I1 falls, output O1 changes after prescribed time, as well.</p> |
