| 摘要 |
PURPOSE: To correct the error of encoding data at high speed by simultaneously multiplying the values of the respective terms of degrees in register output by the original degrees of plural finite fields and adding the degree multiplication result by values corresponding to respective stages. CONSTITUTION: An initial value is set in registers 10 to 12. Addition circuits 61 and 65 add the outputs of the registers 10 to 12 as to the value of the initial value as the addition processing of a first stage so as to calculate the value of an error position equation. The output value of the register 10 is multiplied byα<2> in a multiplication part 14, and the output value of the register 11 is multiplied byαin a multiplication part 19 and they are added in an addition circuit 62 as the addition processing of a second stage and an added result is obtained by adding constant values which the register 12 holds in a circuit 66 so as to calculate the value of an error position equation as the addition processing of a second stage. Then, four degrees can simultaneously be tested as the outputs of addition circuits 65 to 68 in the same way for the rest, Thus, four tests are repeated to code length N.
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