| 摘要 |
PCT No. PCT/JP93/00118 Sec. 371 Date Dec. 30, 1993 Sec. 102(e) Date Dec. 30, 1993 PCT Filed Feb. 2, 1993 PCT Pub. No. WO93/15462 PCT Pub. Date Aug. 5, 1993.A failure analysis memory (7) having main and sub failure analysis memories (7a, 7b) has two counters (C1, C2), a multiplexer (MUX), two registers (RG1, RG2)and a comparator 14. A value corresponding to the size of a column address of a memory under test (2) is set in the register (RG1) and a stop address is set in the register (RG2). Each time a SAM part (2b) of the memory under test sequentially outputs data in an address area specified by a transfer row address and a start address, one of the counters is incremented on a one-by-one basis from a start address set therein, and its count value is selected by the multiplexer (MUX) and output as a sub address signal (SA'). During this time, the other counter in the non-counting state loads therein a main address specifying data that a RAM part 2a transfers next. When the memory under test operates in a simple read/transfer mode or a split read/transfer mode, a column address in the output from the multiplexer (MUX) is compared by the comparator (14) with the value set in the register (RG1). When the memory under test operates in a stop control split read/transfer mode the column address is compared with the value set in the register (RG2). When coincidence is detected by the comparator (14), a controller (12) switches the counting and non-counting states of the counters (C1, C2). |
