发明名称 |
Method for the implementation of Montgomery modular reduction |
摘要 |
Two double-entry multiplexers (41,42) supply shift registers (10,12) and allow entry of a modulo (N) and initiating bits (O). A subtracting circuit (27) has one input connected to the output of one register (10) and the other connected to the output of a multiplexer (36). The multiplexer (36) has one input connected to earth and the other to the output of the second shift register (12). The inputs are selected by a signal (SC) from a circuit (44) which stores comparisons and is supplied from a subtraction unit (40) and gate (43). |
申请公布号 |
EP0712072(A1) |
申请公布日期 |
1996.05.15 |
申请号 |
EP19950470039 |
申请日期 |
1995.10.26 |
申请人 |
SGS-THOMSON MICROELECTRONICS S.A. |
发明人 |
MONIER, GUY |
分类号 |
G06F7/72;G06F11/10;G06F17/10;G09C1/00;H03M13/00;H04L9/10 |
主分类号 |
G06F7/72 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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