Mémoire de masse chiffrante du type embarquable et procédé de protection des informations enregistrées dans cette mémoire.

摘要

The memory has the memory circuits (18) connected by an addressing unit (16) to both an input interface (10) and an output interface (20). A management and control circuit (22) is connected to both the input and output interfaces. An encryption circuit (24) is placed between the input interface and the addressing unit, and is connected to the controller (22). The encryption circuit includes parallel circuits that process multiple bit words transmitted by the input interface at a frequency adapted to the frequency of operation of the encryption circuit. The encryption circuit uses pipe line or overlap architecture. A pseudo-random generator in the encryption circuit provides encryption keys.