Random access memory and an improved bus arrangement therefor

摘要

The present invention is a bus arrangement for a wide I/O Random Access Memory (RAM). The bus arrangement includes a global address bus which drives row/column predecoders and redundancy comparators placed at each edge of the memory array. Two banks of sixteen data I/O (DQs), one bank for each half chip, are placed at either end of the chip providing up to a x32 I/O organization. The main Read/Write Data lines (RWD) are more densely populated near the chip edge than the chip center to provide x4 and x8 options, as well. A local address bus is in the open space between the RWDs to redrive the global address lines at their quarter points.