发明名称 |
PLL circuit having a multiloop, and FM receiving method and apparatus able to utilize the same |
摘要 |
The PLL circuit provides both the advantages of analog phase control, in which a good C/N ratio can be realized, and the advantages of digital phase control, in which broad-band lock can be performed. A multi-channel FM receiving method and apparatus are able to utilize the PLL circuit to reduce the influence of the leakage occurring among input signals and suppress image disturbance. One PLL circuit includes: a VCO; a pre-scaler for dividing a feedback signal obtained from the VCO; a first distributor for distributing the feedback signal to send first and second digital feedback signals; a second distributor for distributing a reference signal to send a digital reference signal and an analog reference signal; a digital phase comparator for comparing the digital reference signal and the first digital feedback signal with each other to send a digital phase error signal; a charge pump; a mixer for adding the digital phase error signal to an analog phase error signal, which is obtained by comparing the analog reference signal with the second digital feedback signal to send a composite phase error signal; and a low-pass filter for eliminating high frequency components from the composite phase error signal to input the resultant signal to the VCO.
|
申请公布号 |
US5517685(A) |
申请公布日期 |
1996.05.14 |
申请号 |
US19940227125 |
申请日期 |
1994.04.13 |
申请人 |
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD. |
发明人 |
AOYAMA, SYUJI;FUNAHASHI, TAKAO;KUBO, KIYOSHI;OKAWA, YASUHITO;SATO, TAKESHI;TAKAHASHI, HIROSHI |
分类号 |
H03L7/087;(IPC1-7):H04B1/16;H03L7/08;H03L7/099 |
主分类号 |
H03L7/087 |
代理机构 |
|
代理人 |
|
主权项 |
|
地址 |
|