MULTIPROCESSOR DEVICE COMPRISING A CLOCK SYNCHRONIZATION DEVICE

摘要

A multiprocessor device comprises a plurality of processors (p1, p2, p3, p4), which mutually synchronously execute the same activities. In such a device it is highly important that the processors (p1, p2, p3, p4) be supplied with mutually synchronized clock signals (clk1, clk2, clk3, clk4). For this purpose, the multiprocessor device according to the invention comprises a clock synchronization device (cir) which comprises a plurality of clock circuits (1, 2, 3, 4). The clock signals (clk1, clk2, clk3, clk4) generated by the clock circuits (1, 2, 3, 4) are fed back. The feedback clock signals (clk1, clk2, clk3, clk4) are applied in each clock circuit (1, 2, 3, 4) to a control signal generator means (CSGM1, CSGM2, CSGM3, CSGM4). This control signal generator means comprises at least two phase comparators (PHI12, PHI13,...,PHI43) for generating phase error signals (V12, V13,...,V34) in response to at least three feedback clock signals. The control signal generator means (CSGM1, CSGM2, CSGM3, CSGM4) further comprises a combining means (CMB1, CMB2, CMB3, CMB4) for combining the phase error signals (V12, V13,...,V34) to a control signal (V1, V2, V3, V4). Each clock circuit also includes a clock signal generator (VC01, VC02, VC03, VC04) which readjusts, as required, a clock signal (clk1, clk2, clk3, clk4) in dependence on the control signal (V1, V2, V3, V4). A clock synchronization device according to the invention is advantageous in that, as conditions dictate, even with a plurality of malfunctioning clock circuits (1, 2, 3, 4), mutually synchronized clock signals (clk1, clk2, clk3, clk4) can nevertheless be produced.