FERROELECTRIC MEMORY

摘要

A non-volatile integrated circuit memory (10, 11, 100, 200) in which the memory cell (10, 11) includes a first transistor gate (19, 36) overlying a first channel region (44A), a ferroelectric material (48) overlying a second channel region (44B), and a second transistor gate (23, 37) overlying a third channel region (44C). The channel regions (44A, 44B, 44C) are connected in series, and preferably are contiguous portions of a single semiconducting channel (44). The first channel (44A) is connected to a plate voltage that is 20 % to 50 % of the coercive voltage of the ferroelectric material. A sense amplifier (110) is connected to the third channel region (44C) via a bit line (108). The rise of the bit line after reading a logic "1" state of the cell is prevented from disturbing the ferroelectric material by shutting off the third channel before the sense amplifier rises.