| 摘要 |
PURPOSE: To realize a high speed initial value indication type frequency synthesizer used for the FH system of the SS communication system in which a low bit A/D converter is employed and a maximum hopping speed is increased up to a fr/2 (fr is a frequency of a reference frequency signal). CONSTITUTION: The loop is tentatively made open in the hopping state and an initial value of a PLL is received from a RAM 16, a difference ΔV between the initial value and a 1st phase measurement value this time is latched and added to a 2nd phase measurement value to update a content of the RAM 16 and it is used for an initial value used when the same frequency is hopped at a succeeding time. In the case of measuring the initial value, when a 1st frequency division signal FV is obtained from a reference signal FR, a frequency division ratio of the frequency divider is set small to provide a delay of nearly π/4, then a phase deviation in a VCO is eliminated. |
