发明名称 METHOD OF REDUCING ELECTRIC CHARGE ON WAFER
摘要 PURPOSE: To minimize the electric charge on a wafer in a plasma CVD or plasma etching apparatus. CONSTITUTION: A reaction furnace housing 1 houses a susceptor 2 and gas jet part 3 surrounded by an insulating cylinder 7 having notches 71 and 72 not obstructing a flow of reacted gas G' exhausted from exhaust holes 14, access to a wafer 5 through an openable window 12 and interior observation through a glass window 13. With applied high frequency voltage±V, electric charges produced at the wafer laid on a uniformly heating disc 21 disperse to the cylinder 7, thereby reducing the attraction of the wafer 5 to the disc 21. This facilitates the wafer to be pulled out of the furnace and avoids damaging the gate, etc., due to the electric discharge of the charges Q.
申请公布号 JPH08115884(A) 申请公布日期 1996.05.07
申请号 JP19940275889 申请日期 1994.10.14
申请人 HITACHI ELECTRON ENG CO LTD 发明人 SAWADA HITOSHI
分类号 C23C16/50;C23F4/00;H01L21/205;H01L21/302;H01L21/3065;(IPC1-7):H01L21/205;H01L21/306 主分类号 C23C16/50
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