| 摘要 |
Disclosed is a bus driver circuit that dynamically clamps the bus voltage for a predetermined period following a transition of the bus voltage, thereby reducing overshoot and ringing. The disclosed circuit dynamically clamps the initial overshoot at approximately the bus terminating voltage VT. The clamping is dynamic in that it is active for only a limited, prescribed period, which is adjustable. In a preferred embodiment, a driver receives an input signal (VIN) and provides an OUTPUT signal to a bus terminated with a terminating voltage (VT). A clamp circuit receives a CLAMP GATE signal and sinks current from the OUTPUT signal, thus reducing ringing and overshoot of the output signal. A delay circuit disables the clamp after a prescribed delay following a transition of the OUTPUT signal.
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