发明名称 LOGIC CIRCUIT
摘要 PURPOSE: To correct a timing deviation in noninverting/inverting data and to correct a duty ratio to be 0.5. CONSTITUTION: An input terminal of an inverter 21 connects to a data input terminal receiving data D and an input terminal of an inverter 22 connects to a data input terminal 12 receiving inverting data D. An output terminal of the inverter 21 connects to a node 13 and an output terminal of the inverter 22 connects to a node 14. An output terminal of the inverter 23 and an input terminal of inverters 24, 25 are connected to the node 13. An output terminal of the inverter 24 and an input terminal of inverters 23, 26 are connected to the node 14. An output terminal of the inverter 25 connects to a data output terminal 15 of the circuit and an output terminal of the inverter 26 connects to a data output terminal 16 of the circuit.
申请公布号 JPH08116242(A) 申请公布日期 1996.05.07
申请号 JP19940273062 申请日期 1994.10.13
申请人 NEC CORP 发明人 NUMATA KEIICHI
分类号 H03K5/04;H03K3/017;H03K5/151;H03K19/003 主分类号 H03K5/04
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